This invention relates to a digital data processing system, and more specifically to a memory for use in such a data processing system.
In general a digital data processing system has three basic elements: namely, a central processor, a memory arrangement for storing programs and data for manipulation by the central processor, and input/output units for communicating with the central processor and memory arrangement. One important aspect of a memory arrangement is the dependence of the overall speed of the system on the operation of the memory arrangement. For example, if a memory arrangement performs a memory cycle to retrieve data from a location therein in 1.2 microseconds (i.e., its characteristic retrieval interval), the minimum time required to process an instruction is 1.2 microseconds. As two or more memory cycles are often required in order to process an instruction, the average time for processing each of successive instrucation will be greater than the 1.2 microsecond characteristic retrieval interval.
Thus, in order to enable the data processing system to operate at the greatest possible speed, it is necessary to minimize the characteristic retrieval interval for the memory arrangement. However, memory cost generally increases as the characteristic retrieval interval is reduced. Therefore, the entire memory arrangement usually can not be constructed from fastest elements because its costs would be prohibitively high.
A memory arrangement for a data processing system thus may contain several types of memory units that have diverse characteristics. Each type has particular characteristics that make it suitable for specific applications. Generally a digital data processing system includes a random access memory unit. The time required to obtain information from a random access memory unit is independent of the lcoation of the information most recently obtained. Such memory units have included magnetic cores or solid state devices as the storage elements. Magnetic core memory units are very popular because they are reliable and retain data even in the absence of electrical power. Their characteristic retrieval intervals are usually measured in terms of one or two microseconds. Semiconductor random access memory units are considerably faster than magnetic core memory units and have characteristic retrieval intervals on the order of hundreds of nanoseconds. However, they require constant electrical power to retain data. If the electrical power is interrupted, the contents are lost. Both types of random access memory units have similar costs and in some data processing systems they constitute the entire memory arrangement.
Direct access memory units include, conventionally, disk and drum memory units. Their characteristic retrieval intervals are slower than random access memory units and are measured usually in terms of milliseconds. However, they are able to store relatively large amounts of data at costs that are significantly less than the costs of storage in random access memory units. Generally a direct access memory unit is used to supplement the random access memory unit. In many memory arrangements, the contents of the two memory units are constantly being interchanged in order to provide the most rapid data processing operations with a minimum random access memory unit storage capability.
Sequential access memory units, such as magnetic tape memories, constitute another type of memory unit. These memory units often are used for archival storage or to provide a "copy" of the contents of the random access and direct access memory units. They have even longer characteristic retrieval intervals than direct access memory units have, but the storage costs again are significantly lower.
As previously indicated, a particular memory arrangement in a data processing system may include two or more of these memory units in combination. A typical memory arrangement might include a magnetic core random access memory unit and a direct access memory unit.
A more recent configuration includes both semiconductor random access memory units and magnetic core random access memory units. One such system is described in the foregoing U.S. Pat. No. 4,016,541. In this system the central processor normally communicates with various input/output devices and a magnetic core random access memory unit over an asynchronous bus. However, the central processor also transfers data to and from a semiconductor memory unit over a second bus to provide increased operating speeds. Typically the semiconductor memory unit has sufficient capacity to store a complete program or a significant portion of such a program.
All the foregoing memory units transfer data to or form locations identified by address signals. Another type of memory unit is an associative, or content-addressable, memory unit. In such a memory unit a location is selected on the basis of what it contains and not on the basis of its address. An associative memory unit is useful in several applications. For example, in a machine that utilizes virtual addresses, each location in the memory unit contains both a virtual address and the corresponding address for the actual location. Such a system is described in the foregoing U.S. Pat. No. 3,893,084.
Other systems combine an associative memory unit as a "cache" memory unit for storing small portions of a program. Each time the central processor issues a memory address using a memory retrieval cycle, the associative memory unit searches to determine whether an address storage location contains that address. If it does, data in a corresponding data storage location in that memory unit is immediately transferred to the central processor. If it does not, the contents of that location in the random access memory unit identified by the address, as well as data from a block of successive locations, are transferred to the associative memory unit. This memory arrangement can improve the overall speed of the memory whenever the data is contained in the associative memory unit because the memory operates with the speed of a semiconductor memory.
Given a specific combination of memory units, shorter characteristic retrieval intervals also can be attained by other methods. For example, the memory arrangement may include memory units that are divided into separate elements or banks so that sequential memory cycles in different elements can be "overlapped". One such memory arrangement that is described in the foregoing U.S. Pat. No. 3,810,110, contains memory units of different characteristic retrieval intervals, all connected to a common memory bus. However, separate memory retrieval control signals are required, so the operating programs for the central processor must determine which memory retrieval control signal is to be sent to initiate each memory cycle.
Therefore, it is an object of this invention to provide a memory system for a data processing system that enables overlapped transfers without the need for multiple control signals.
Another object of this invention is to provide a memory arrangement for a data processing system that contains diverse types of memory units combined in a cost effective manner.
Still another object of this invention is to provide a memory arrangement that can obtain random access memory units having diverse characteristics.
Yet another object of this invention is to provide a random access arrangement that is adapted for interleaved operation.
Still yet another object of this invention is to provide a memory arrangement including magnetic core memory units that has an average characteristic retrieval interval that is less than the characteristic retrieval interval for magnetic core memory units.